LATW 2006 - Call for Participation

CALL FOR PARTICIPATION

Technical Program

Sunday - March 26th, 2006
8:00–9:00	LATW’06 and TTEP’06 Registrations
18:30–20:00	LATW’06 Registration
IEEE Computer Society Test Technology Educational Program (TTEP)
9:00–13:00	Tutorial 1: “Memory Test and Self-Test for Deep Submicron Technologies,” Dean Adams, Magma Design Automation - USA
14:30–18:30	Tutorial 2: “Design for Manufacturability,” Yervant Zorian, Virage Logic - USA; Juan-Antonio Carballo, IBM - USA
Monday - March 27th, 2006
7:30–8:30	LATW’06 Registration
8:30–9:00	Opening Address LATW’05 Best Paper Award Presentation
9:00-10:35	Session 1: Analog & Mixed Signal Testing and Diagnosis Chair: Gabriela Peretti – Univ. Tecnológica Nacional / Facultad Regional Villa María, Argentina 9:00-9:15: [S] Timed Functional Modeling For Mixed-Signal Boards in Maintenance Testing Bertrand Gilles, Valérie-Anne Nicolas, Laurent Lemarchand, Lionel Marcé - University of Western Brittany, France 9:15-9:35: Improved Fault Detection Using a Charge Monitor Rodrigo Picos - Balearic Islands University, Spain; Oscar Calvo - UNLP, Argentina; Miquel Roca, Eugeni Garcia-Moreno - Balearic Islands University, Spain 9:55-10:15: On the Testing of the Electronic Conditioning Chain of a CMOS MEMS Based Magnetic Field Sensor Olivier Leman, Florence Azais, Laurent Latorre, Frédérick Mailly, Pascal Nouet - LIRMM, Univ. Montpellier II/CNRS, France 10:15-10:35: Using Swarm Intelligence to Solve Some Analog Test Issues Carlos Eduardo Savioli - Brazilian Navy Electronics Center, Brazil; Claudio Eduardo Csura Szendrodi, José Calvano - IPqM, Brazil; Antônio Mesquita Filho - UFRJ, Brazil
10:35-10:55 Coffee Break
10:55-11:50	Session 2: SAT Solvers and Functional Verification Chair: Abhijit Chatterjee – Georgia Tech, USA 10:55-11:15: Integrating Observability Don't Cares in All-Solution SAT Solvers Sean Safarpour, Andreas Veneris - University of Toronto, Canada; Rolf Drechsler - University of Bremen, Germany; Magdy Abadir - Freescale, USA 11:15-11:35: Cube Subtraction in Sat Solvers Romanelli Zuim - UFMG, Brazil; Jose T. Sousa - INESC-ID, Lisboa, Portugal; Claudionor N. C. Júnior - UFMG, Brazil 11:35-11:50 [S] An Approach for Debugging and In-system Functional Verification for FPGA-based System Design John Michael Espinosa-Duran, Mario Vera-Lizcano, Jaime Velasco-Medina - Universidad del Valle, Colombia
11:50-12:45	Session 3: Timing Analysis and Verification Chair: Carlos Silva Cardenas – PUCP, Peru 11:50-12:10: Automatic Evaluation of Single Event Transient Propagation in CMOS Logic Circuits Based on Topological Timing Analysis Carolina Neves - UFPel, Brazil; Egas Henes Neto, Ivandro Ribeiro, Gilson Wirth - UERGS, Brazil; Fernanda Kastensmidt - UFRGS, Brazil; Jose Luis A. Guntzel - UFPel, Brazil 12:10-12:25: [S] High-level Automatic Verification Methodology for Computer Graphics Cores Fabricio V. Andrade, José Augusto Nacif, Claudionor N. Coelho Jr., Antônio O. Fernandes - UFMG, Brazil 12:25-12:45: Oscillation-Based Test in Digital IIR Filters Gabriela Peretti, Eduardo Romero - Universidad Tecnológica Nacional Facultad Regional Villa María, Argentina; Carlos Marqués - Universidad Nacional de Córdoba, Argentina
12:45-14:00 Lunch
14:00-15:40	Session 4: BIST and On-line Testing Chair: Lorena Anghel – TIMA/INPG, France 14:00-14:20: Using Bulk Built-In Current Sensors to Detect Transient Faults in SRAM Memory Architectures Egas Henes Neto, Gilson Wirth - UERGS, Brazil; Fernanda Lima Kastensmidt - UFRGS, Brazil 14:20-14:40: Concurrent Testing of Digital Circuits for Non-Classical Fault Models: Bridging Faults and n-Detect Test Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra - IIT Kharagpur, India 14:40-15:00: Software Based Self-Test of Register Files in RISC Processor Cores using March Algorithms Matthieu Tuna, Mounir Benabdenbi - University of Pierre et Marie Curie, France 15:00-15:20: Testing System-in-Package Wirelessly Serge Bernard, Marie-lise Flottes, LIRMM, France; Philippe Cauvet, Hervé Fleury, Fabrice Verjus - Philips France Semiconducteurs, France 15:20-15:40: BIST Architectures and Fault Emulation Abílio Eduardo Mendes Parreira, Marcelino Santos, João Teixeira - Instituto Superior Técnico/INESC-ID, Portugal
15:40-16:00 Coffee Break
16:00-17:20	Session 5: DFT and Fault Injection Techniques Chair: Janusz Sosnowski – Warsaw Univ. of Tech., Poland 16:00-16:20: Scan Pattern Watermarking David Hély, Frédéric Bancel - ST Microelectronics, Rousset, France; Marie-lise Flottes, Bruno Rouzeyre - LIRMM, France 16:20-16:40: A Secure Scan Design Methodology David Hély, Frédéric Bancel, ST Microelectronics, Rousset, France; Marie-lise Flottes, Bruno Rouzeyre - LIRMM, France 16:40-17:00: A Fault Injection Environment for SoPC’s Embedded Microprocessors Marta Portela-Garcia - Universidad Carlos III de Madrid, Spain; Luca Sterpone - Politecnico di Torino, Italy; Celia Lopez-Ongil - Universidad Carlos III de Madrid, Spain; Matteo Sonza Reorda, Massimo Violante - Politecnico di Torino, Italy 17:00-17:20: DefSim: CMOS Defects on Chip for Research and Education Witold Pleskacz, Tomasz Borejko, Andrzej Walkanis - Warsaw University of Technology, Poland; Viera Stopjakova - Slovak University of Technology, Slovakia; Artur Jutman, Raimund Ubar - Tallinn University of Technology, Estonia
17:30-19:00 Welcome Reception
19:15-20:15	LA-TTTC Group Open Meeting
Tuesday - March 28th, 2006
8:30-9:30	Session 6: Fault Modeling, Analysis and Simulation - I Chair: Artur Jutman - Tallinn University of Technology, Estonia 8:30-8:50: FPGA-Based Stuck-at Fault Emulation in Wavelet-based Image Coding Systems Lucia Costas-Perez, Juan Rodriguez-Andina, Elena Lago - University of Vigo, Spain 8:50-9:10: Analyzing the Effect of CMOS Process Variability on the SRAM Cell Sensitivity to SEU Jean Da Rolt - UFRGS, Brazil Gilson Wirth - UERGS, Brazil Fernanda Kastensmidt, Ricardo Reis - UFRGS, Brazil 9:10-9:30: Evaluating the Sensitivity of CMOS Circuits to Single Event Transients Gilson Wirth, Michele Vieira, Egas Henes Neto - UERGS, Brazil Fernanda Kastensmidt - UFRGS, Brazil
9:30-10:50	Session 7: Fault Modeling, Analysis and Simulation - II Chair: Zebo Peng - Linkoping University, Sweden 9:30-9:50: Exploring and Interpreting System Event Logs Janusz Sosnowski, M. Poleszak - Warsaw University of Technology, Poland 9:50-10:10: Fault Simulation with Parallel Critical Path Tracing for Combinational Circuits Using Structurally Synthesized BDDs Sergei Devadze, Jaan Raik, Artur Jutman, Raimund Ubar - Tallinn University of Technology, Estonia 10:10-10:30: Using Multiple Clock Schemes and Multi-Temperature Test for Dynamic Fault Detection in Digital Systems Marcial Jesús Rodríguez Irago, Juan Rodriguez-Andina - University of Vigo, Spain; Fabian Vargas - PUCRS, Brazil; Isabel Teixeira, João Teixeira - INESC-ID, Portugal 10:30-10:50: Enhancing the Detectability of Open Defects by Body Biasing Antonio Zenteno Ramirez, Roberto Gomez, Victor Champac - INAOE, Mexico
10:50-11:10 Coffee Break
11:10-12:30	Session 8: SEU Modeling and Simulation Chair: Kaushik Roy – Purdue University, USA 11:10-11:30: Validation by Fault Injection of a Software Error Detection Technique Dealing with Critical Single Event Upsets Gustavo Santana Torrellas - Instituto Mexicano del Petroleo, Mexico; B. Nicolescu - Institut Polytechnique de Montreal, Canada; M. G. Valderas - Universidad Carlos III, Spain; Raoul Velazco, Y. Savaria - TIMA Laboratory, France 11:30-11:50: [S] Obtaining Markoff Models For Dependability Estimation in Fault Tolerant Systems Exposed to SEUs Pablo A. Ferreyra - Universidad Nacional de Córdoba / Instituto Universitario Aeronáutico de Córdoba, Argentina; Carlos A. Marqués - Facultad de Matemática, Astronomía y Física, Universidad Nacional de Córdoba, Argentina; Ricardo T. Ferreira - Facultad de Ciencias Exactas Físicas y Naturales Universidad Nacional de Córdoba, Argentina; Gabriel Viganotti - Facultad de Matemática, Astronomía y Física, Universidad Nacional de Córdoba, Argentina 11:50-12:10: SEU Effects Evaluation on a NoC Router Architecture Arthur Frantz, Fernanda Kastensmidt - UFRGS, Brazil 12:10-12:30: Study of Single Event Upset Effects in SRAM-Based Field Programmable Analog Arrays Tiago Balen, Marcelo Lubaszewski - UFRGS, Brazil; Michel Renovell – LIRMM, France
12:30-14:00 Lunch
14:00-16:30	Embedded Tutorials Slot 14:00-14:50: Tutorial 1: Process Variations: It’s Impact on Design and Test of CMOS Circuits Presenter: Kaushik Roy - Purdue University, USA; Coordinator: Raoul Velazco – TIMA/INPG, France 14:50-15:40: Tutorial 2: ATPG-Based Techniques for Verification Presenter: Dirhaj Pradhan - Bristol University, UK; Coordinator: Marcelino Santos – IST / INESC-ID, Portugal 15:40-16:30: Tutorial 3: Parametric Failures and Detection Strategies Presenter: Chuck Hawkins - University of New Mexico, USA; Coordinators: Victor Champac – INAOE, Mexico; Florence Azais – LIRMM, France
16:30-16:50 Coffee Break
16:50-17:50	Session 9: High-Level Testing, Verification and Validation Chair: Fernanda L. Kastensmidt – UFRGS, Brazil 16:50-17:10: Signaling Chip Errors with SNMP Fabrício Damasceno, José Augusto Nacif, Rodrigo Passos, Antônio O. Fernandes, Claudionor N. Coelho Jr. - UFMG, Brazil 17:10-17:30: An Optimal Test Assignment for Monitoring General Topology Networks Andréa Weber, UTFPR - Brazil; Elias Procópio Duarte Jr. - UFPR, Brazil; Keiko Verônica Ono Fonseca - UTFPR, Brazil 17:30-17:50: Off-line Synchronization of Distributed Logs in Fault Injection Test Campaigns Joana Trindade, Gabriela Jacques-Silva, Roberto Jung Drebes, Taisy Weber, Ingrid Jansch-Pôrto - UFRGS, Brazil
19:30-23:30 Social Event: Piazzola Tango (www.piazzollatango.com)
Wednesday - March 29th, 2006
8:30-9:50	Session 10: SEU-Hardening Approaches Chairs: José Luís Guntzel – UFPEL, Brazil; Marie-lise Flottes – LIRMM, France 8:30-8:50: A New Approach to Cope with Single Event Upsets in Processor-Based Systems Massimiliano Schillaci, Matteo Reorda, Massimo Violante - Politecnico di Torino, Italy 8:50-9:10: Using Memory to Cope with Simultaneous Transient Faults Eduardo Rhod, Carlos Lisboa, Luigi Carro - UFRGS, Brazil 9:10-9:30: Design of a Robust 8-Bit Microprocessor to Soft Single Event Effects Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis - UFRGS, Brazil 9:30-9:50: Multiple Defects Tolerant Devices for Unreliable Future Nanotechnologies Lorena Anghel, Cristiano Lazzari, Michael Nicolaidis - TIMA Laboratory/INPG, France
9:50-10:50	Session 11: Software Reliability Estimation Chair: Matteo Sonza Reorda – Politecnico di Torino, Italy 9:50-10:10: An Aspect Oriented Fault Injection Tool to Test Fault Tolerant Mechanisms of Dependable Java-Based Network Applications Karina Kohl, Taisy Weber - UFRGS, Brazil 10:10-10:30: Modeling Software Reliability Growth With Artificial Neural Networks Gustavo de Souza, Silvia Vergilio - UFPR, Brazil 10:30-10:50: Software Dependability Estimation Based on Test Failure Data Jorge Moreira de Souza, Simone G. Schmidt - FITec, Brazil
10:30-10:50 Coffee Break
10:50-12:05	Session 12: Software Verification and Testing Chair: Magdy Abadir – Freescale, USA 10:50-11:10: Test Automation Viability Analysis Method Jorge Corrêa de Oliveira, Cidinha Costa Gouveia, Romulo Quidute Filho - CESAR/Motorola, Brazil 11:10-11:30: Probe Effect Mitigation in the Software Testing of Parallel Systems Leonardo Amaral, Eduardo Bezerra, Flávio Oliveira, Luiz Gustavo Leão Fernandes, Mateus Raeder, Pedro Velho - PUCRS, Brazil 11:30-11:50: Performance Engineering as Part of the Development Life Cycle to Java Applications Flávia Merylyn Falcão - UFPE, Brazil; Rodrigo Elia Assad, Silvio Lemos Meira - CESAR, Brazil 11:50-12:05: [S] Service-Oriented Architecture Testing Design and Practices Alexandre Santos Júnior, Andre Assad, Luiz Felipe S. L. Guimarães - CESAR/Motorola, Brazil
12:05-14:00 Lunch
14:00-15:00	Session 13: Fault Tolerant Architectures and Techniques Chair: Dirhaj Pradhan - Bristol University, UK 14:00-14:20: Defect and Fault Masking in Nanofabric Through Redundancy Adaptation Wenjing Rao, Alex Orailoglu - University of California San Diego, USA Ramesh Karri - Polythecnic University, USA 14:20-14:40: Increasing Reliability in Future Technologies Systems Erik Schuler, Luigi Carro - UFRGS, Brazil 14:40-15:00: Probabilistic Error Correction in Linear Digital Filters Using Checksum Codes Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee - Georgia Institute of Tech., USA
15:00-16:20	Session 14: Radiation Test Facilities and EMI Testing Chair: Oscar Calvo – University of the Balearic Islands, Spain 15:00-15:20: A Radiation Damage Test Facility at TANDAR Martin Alurralde, Julio Durán, Alberto Filevich, Christian Nigri, Igor Prario, Felix Palumbo - Comisión Nacional de Energía Atómica, Argentina; Gerardo Sager - Universidad Nacional de La Plata, Argentina; Raoul Velazco - TIMA Laboratory, France; Alejandro Vertanessian - Comisión Nacional de Energía Atómica, Argentina 15:20-15:40: TANDAR as a Digital Circuits Test Radiation Facility Gerardo Sager - Universidad Nacional de La Plata, Argentina; Martin Alurralde, Igor Prario, Felix Palumbo, Alberto Filevich, Alejandro Vertanessian - Comisión Nacional de Energía Atómica, Argentina; Raoul Velazco - TIMA Laboratory, France; Pablo Ferreyra - Universidad Nacional de Cordoba, Argentina 15:40-16:00: A Thermal Cycling Testing System to Simulate Space Conditions Igor Prario, Alejandro Vertanessian, Alberto Filevich, Martin Alurralde, Claudio Bolzi, Cristián Bruno, Javier Férnandez Vázquez, Mónica Martinez Bogado, Mariana Tamassi, Virgilio Goldbeck, Christian Nigri - Comisión Nacional de Energía Atómica, Argentina 16:00-16:20: Observing SRAM-Based FPGA Robustness in EMI-Exposed Environments Fabian Vargas, Juliano Benfica, Augusto Farina, Eduardo Bezerra - PUCRS, Brazil; Edmundo Gatti, Luis Garcia, Daniel Lupi - INTI/CITEI, Argentina; Fernando Hernandez - ORT/URSEC, Uruguay
16:20-16:40 Coffee Break
16:20-17:40	Session 15: Radiation Hardening Chair: Pablo A. Ferreyra –Universidad Nacional de Córdoba / Instituto Universitario Aeronáutico de Córdoba, Argentina 16:20-16:40: Electrical Stress and Gamma Irradiation of MOS Transistors Felix Palumbo - CONICET-CNEA, Argentina; Adrian Faigon - FIUBA-CONICET, Argentina; Giuseppe Curro - ST Microelectronics, Italy; Igor Prario - CONICET-CNEA, Argentina; Alessandra Cascio - ST Microelectronics, Italy 16:40-17:00: Characteristic Parameters of Simulated PIN Photodiodes under Proton Radiation Marcelo Angel Cappelletti, Eitel Leopoldo Peltzer y Blancá - University of La Plata, Argentina 17:00-17:20: High Energy Heavy Ion-Induced Structural Modifications: From the Material Point of View to New Hardening Concepts A. D. Touboul, M. Marinoni, A. Carvalho, C. Guasch, F. Saigné, J. Bonnet, J. Gasiot - Université Montpellier II, France
17:20-17:40	Closing Remarks

Committees

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ORGANIZING COMMITTEE:

General Chairs:
Fabian Vargas, PUCRS - Brazil
vargas@computer.org

Yervant Zorian, Virage Logic - USA
yervant.zorian@viragelogic.com

Honorary Chair:
Daniel Lupi, INTI - Argentina

Past General Chair:
Marcelo Lubaszewski, UFRGS - Brazil

Program Chairs:
Eduardo Bezerra, PUCRS – Brazil
Victor Champac, INAOE - Mexico

Embedded Tutorials Chairs:
Magdy Abadir, Freescale - USA
Zebo Peng, Linkoping Univ. - Sweden

Panels Chairs:
Luigi Carro, UFRGS – Brazil
José Vicente Calvano, Braz. Navy – Brazil

TTEP Tutorials Chair:
D. Gizopoulos, Univ. of Piraeus – Greece

Publicity Chairs:
José Luis Huertas, IMSE / CNM - Spain
Marius Strum, USP - Brazil

Publication Chair:
Júlio Leão, PUCRS – Brazil

Industry Liaison:
César Dueñas, Freescale – Brazil

IEEE Design & Test Liaison:
K. Roy, Purdue Univ. – USA

Local Arrangements Chair:
Liliana Fraigi, INTI - Argentina

Asia Liaison:
Yoshio Mita. Univ. of Tokyo - Japan

East Europe Liaison:
R. Ubar, Tallinn Tech. Univ. – Estonia

West Europe Liaison:
M. L. Flottes, LIRMM – France

North America Liaison:
A. Chatterjee, Georgia Tech. – USA

PROGRAM COMMITTEE:

J. Abraham – Univ. of Texas, USA
V. D. Agrawal - Auburn Univ., USA
L. Balado - UPC, Spain
A. Brun - Institut d´Optique, France
O. Calvo - UNLP, Argentina
R. Canetti – UROU, Uruguay
C. S. Cardenas – PUCP, Peru
E. P. Duarte Jr. - UFPR, Brazil
P. Fouillat - IXL Bordeaux, France
M. P. Gough – Univ. of Sussex, UK
J. L. Guntzel – UFPel, Brazil
J. P. de Gyvez, - Philips, The Netherlands
C. W. Hawkins – Univ. of New Mexico, USA
J. P. Hayes - Univ. of Michigan, USA
A. Ivanov – U. B. Columbia, Canada
R. Leveugle – TIMA-INPG, France
M. Linares – INAOE, Mexico
J. C. Maldonado – ICMSC/USP, Brazil
J. V. Medina - Univ. del Valle, Colombia
A. Mesquita – UFRJ, Brazil
F. G. Moraes – PUCRS, Brazil
A. Orailoglu – UCSD, USA
G. Peretti - Fac. Reg. Villa María, Argentina
J. Perez – UROU, Uruguay
D. K. Pradhan – Univ. of Bristol, UK
R. Reis – UFRGS, Brazil
M. Renovel – LIRMM, France
M. S. Reorda - Politec. di Torino, Italy
E. Romero – UTN, Argentina
J. Salcedo – Texas Instruments, USA
A. Sarmiento – INAOE, Mexico
F. Silveira – UROU, Uruguay
M. Soma - Univ. of Washington, USA
J. Sosnowski - Warsaw Univ. of Tech., Poland
A. A. Suzim – UFRGS, Brazil
J. M. de Souza – FITec, Brazil
L. E. Toledo - UCC, Argentina
T. Weber - UFRGS, Brazil
H. J. Wunderlich – Univ. Stuttgart, Germany
A. Zenteno – INAOE, Mexico
A. Zorzo – PUCRS, Brazil

STEERING COMMITTEE:

Victor Champac (Chair)
Jose Luis Huertas
Marcelo S. Lubaszewski
Fabian Vargas
Raoul Velazco
Yervant Zorian

For more information, visit us on the web at: http://www.latw.net

The 7th IEEE Latin American Test Workshop is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) in cooperation with Catholic University – PUCRS, Brazil and the Instituto Nacional de Tecnología Industrial – INTI, Argentina .